In conventional fabrication of semiconductor devices, semiconductor wafers are processed in batch, and a large number of complicated devices are formed on a single wafer. With rapid development of very large scale integration (VLSI), wafers are developed toward higher integration density and miniaturization. In the fabrication process, the critical dimensions of integrated circuits are further reduced as well, which raises a higher requirement for lithography processes. However, due to the restriction by the light source wavelength of conventional immersion scanners, conventional lithography cannot meet requirements of processes below 28 nm. In order to satisfy the requirements of processes below 28 nm, extreme ultraviolet (EUV) lithography techniques are used.
EUV lithography is an emerging technology utilizing extreme ultraviolet light to transfer a circuit layout pattern from a reflective EUV photomask (referred to herein as an “EUV mask” and also commonly referred to as a “reticle”) to a semiconductor die. In one common implementation, the EUV mask includes a substrate, a multi-layer reflector formed over the substrate, and an absorber formed over the reflector. The reflector and the absorber are tuned to be predominately reflective and absorptive, respectively, of extreme ultraviolet light at a chosen EUV wavelength, such as about 13.5 nm. Utilizing conventional lithography, the absorber is patterned to expose selected areas of the underlying reflector corresponding to the desired circuit layout. The remaining portions of the absorber absorb the EUV radiation. During EUV lithography, EUV light is projected through a system of mirrors onto the EUV mask at a slight angle relative to the mask surface normal (commonly referred to as an “angular exposure” or “off-axis illumination”). Reticle masking blades or, more simply, “REMA” blades are commonly included in the exposure system to block the extra radiation outside the active semiconductor devices. The light impinging upon the REMA blades is primarily absorbed; while the light impinging upon the exposed regions of the reflector is primarily reflected from the EUV mask onto a layer of photoresist. The photoresist is utilized to impart the desired circuit layout to the semiconductor die. Leakage of EUV radiation occurs during exposure of adjacent dies. This primarily is caused by residual absorber reflectivity and REMA blade instability and out-of-band light reflections, resulting in over exposure around die edges.
Due to the angular exposure utilized during EUV lithography, a shadow effect occurs wherein small portions of the incoming and outgoing EUV light are inadvertently blocked by the upper sidewall edges of the absorber pattern. As the severity of the shadow effect varies in relation to orientation of the absorber pattern relative to the EUV light, the shadow effect results in a horizontal-to-vertical bias in critical dimensions. The shadow effect can be minimized by reducing the thickness or height of the absorber film; however, this also reduces the absorptivity of the absorber material. Furthermore, this effect is additionally magnified near the edges of the semiconductor die due to the positional inaccuracies of the REMA blades. Additional unwanted EUV light from the REMA blades may reflect an undesirably high amount (e.g., 2-3%) of EUV light at the selected wavelength, in addition to a certain amount of out-of-band light near the periphery of the semiconductor device. Image resolution may thus become blurred or undesirably diffuse at the outer edges of an exposure reflected from the EUV mask. When semiconductor dies are sequentially printed utilizing such an EUV mask, the dies may be overexposed multiple times along their neighboring edges resulting in uncontrolled variations in the critical dimensions.
One solution proposed to reduce the reflectivity of EUV masks along the regions surrounding the patterned area of the EUV mask forms a non-reflective or “black” border around the die pattern area. In this proposed solution, the reflector is physically removed along the die pattern border utilizing, for example, a plasma etch. While effectively eliminating reflectivity at the die pattern border, this solution requires precise removal of the border region, a relatively large area. Heretofore, EUV mask processing has not achieved sufficiently precise removal of the border region at acceptable processing rates, i.e., patterning or removal of the border of EUV masks presents a bottleneck in the EUV mask fabrication process.
Accordingly, it is desirable to provide embodiments of an improved extreme ultraviolet (EUV) mask fabrication process wherein the reflectivity of EUV light along the die pattern border is minimized by removing an EUV mask border region in a manner that requires relatively less time while providing sufficient precision. It would further be desirable to provide embodiments of a method suitable for fabricating an integrated circuit utilizing such an extreme ultraviolet (EUV) mask. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.